Two-exposure phase shift photolithography with improved inter-feature separation

ABSTRACT

A method of double-exposure photolithography of a semiconductor wafer in the manufacture of integrated circuits is disclosed. The two exposures of the same positive photoresist layer are carried out using a binary photomask ( 25 ) having chrome regions ( 22 ) that define non-critical dimension features ( 6   c ) and also serve as protection for phase shift exposure of critical dimension features ( 6   g ). The phase shift photomask ( 23 ) includes apertures  20   0   , 20   π , that expose the sides of the critical dimension feature ( 6   g ) with opposite phase light. The phase shift photomask ( 23 ) also includes an additional aperture ( 30 ) for double exposure of a region exposed by the binary photomask, for example as between a non-critical dimension feature ( 6   c ) and the end of a critical dimension feature ( 6   g ). According to another disclosed feature, orthogonal overlapping chrome regions ( 34, 36 ), each of critical dimension width (w 34 , w 36 ), are provided on the binary and phase shift photomasks ( 35, 33 ), to define a feature by way of their intersection.

BACKGROUND OF THE INVENTION

[0001] This invention is in the field of integrated circuitmanufacturing, and is more specifically directed to photolithographyprocesses in such manufacturing.

[0002] As is fundamental in the field of integrated circuit electronics,the functional capability of an integrated circuit depends substantiallyupon the number of active components (transistors, resistors,capacitors, etc.) that can be physically realized per unit area of theintegrated circuit. It is therefore desirable to fabricate devicefeatures that are as small as possible, and as closely packed aspossible, to provide not only a high level of functionality for theintegrated circuit, but also a high level of circuit performance due tosuch small feature sizes. For example, many modern integrated circuitdevices are fabricated with lateral features that are below one-halfmicron in width, realizing as many as tens of millions of transistors ina single integrated circuit operating at clock frequencies greater than100 MHz. It is contemplated that these trends toward smaller and fasterdevices will continue, to the extent permitted by the state of the artof the manufacturing technology.

[0003] Conventional integrated circuit manufacturing technology utilizesphotolithography for defining the location and dimensions of lateralfeatures in the integrated circuit. As is fundamental in the art,photolithography is generally carried out by the application of aphotosensitive substance, referred to as photoresist, over the film tobe patterned. Selective exposure of the photoresist to electromagneticenergy (i.e., light) defines the portions of the film that are to beremoved by the developing process, and those locations that are toremain.. For purposes of manufacturing efficiency, the photoresist overthe full area of one or more of the integrated circuits on the wafer aresimultaneously exposed through photomasks, with transparent and opaqueregions of the photomasks defining the locations of the photoresist thatare exposed or not exposed, respectively. As a result of developing,photoresist is removed from the surface of the wafer, with the remainingregions of the photoresist (as defined by the selective exposure)serving as a mask to the etch of the underlying film, thus defining thefeatures of the integrated circuit. Such masking may also be used inconnection with other processes, such as ion implantation. Once the etchis completed, the remaining photoresist mask is then removed from thewafer. The processing of the wafer continues, with deposition of thenext film layer and, if desired, photolithographic patterning andetching of this next layer.

[0004] According to modern conventional technology, the photomasks aregenerally in the form of reticles, where the images on the photomaskitself are of some multiple magnitude (e.g., 4X) of the feature size tobe patterned on the wafer. Exposure of the wafer through the reticle iscarried out in combination with a focusing lens system disposed betweenthe reticle and the wafer, so that the patterned exposure is reducedfrom that on the reticle. Reticles are generally used in connection withstepper exposure systems, in which only one or a few integrated circuitdie are exposed at a time; the wafer is then indexed, or “stepped”, tothe next position for photo-exposure through the reticle. The largerfeature sizes on the reticles, relative to the integrated circuitfeature sizes, facilitates the fabrication of the reticles themselves byway of photolithography. Of course, the photomasks may alternatively beso-called 1X photomasks that are placed in proximity to the wafer beingpatterned. For purposes of this description the term photomask willrefer both to 1X photomasks and also to reticles, of both the full waferand stepper type.

[0005] Certain “critical dimension” features in the integrated circuit,such as transistor gate electrodes, contact aperture sizes, andconductor widths and the like, relate directly to the density andperformance of the integrated circuit. Typically, minimum widthtransistor gate electrodes are the most critical features in theintegrated circuit layout, given the prevalence of transistors in theintegrated circuit and also considering that gate electrode widthrelates directly to transistor channel length and thus to the gain andswitching speed of the device. As such, the ability to reliably defineand construct ever-smaller features such as transistor gates is of highimportance in the field of integrated circuit design and manufacture.

[0006] As noted above, critical dimension features of modern integratedcircuits are now on the order of one-half micron or less. Suchsub-micron critical dimensions are on the order of the wavelength of thelight energy used in the exposure. At these dimensions, the minimumfeature size that may be imaged, at a usable depth of focus, dependsstrongly upon the wavelength of light used; so-called “deep UV” light iscurrently used to effect the higher resolution imaging required formodern integrated circuits. In modern photolithography processes, theminimum feature size that may be imaged by a photomask is approximately${0.5\frac{\lambda}{NA}},$

[0007] where X is the wavelength of the exposing light and NA is thenumerical aperture of the lens system of the stepper. Theproportionality constant of this resolution ratio (in this example,having the value 0.5) is commonly referred to in the art as k₁; asimilar relationship is provided for depth of focus (having aproportionality constant k₂). While a large numerical aperture permitsthe patterning of extremely small features, the depth of focus of thelens system decreases with increasing NA values. Considering therealistic extent to which the topography of the wafer can be made flatduring its manufacture, which in turn limits the numerical aperture ofthe lens system, the minimum feature size that can be patterned byphotolithography at a given wavelength reaches a practical limit.

[0008] Certain techniques for further reduction in the feature size thatmay be imaged for a given wavelength are also known in the art. Oneknown technique uses a phase-shift photomask in which adjacent or nearbyopenings, or apertures, transmit light at opposing phases (i.e., 0° and180° ). As known in the art, light passing through a mask aperture of asize on the same order as the wavelength of the light will be locallycoherent. The phase of this locally coherent light depends upon thethickness of the transparent material through which the light passes; assuch, phase shift photomask apertures have varying thicknesses relativeto one another, to establish the phase shift relationship. The phaseshift effect may be used to define extremely small features on the waferby placing opposite phase apertures on opposite sides of the smallfeature to be defined. To the extent that diffracted light reaches thephotoresist at the location of the feature from both of the oppositephase apertures, the opposing phases will tend to cancel one another. Asa result, unintended exposure of critical feature locations is greatlyreduced, permitting the formation of these features.

[0009] Examples of conventional phase-shift photolithography aredescribed in U.S. Pat. No. 5,045,417, U.S. Pat. No. 5,573,980, and U.S.Pat. No. 5,858,580.

[0010] In particular, one conventional approach utilizes two masks inthe photolithographic patterning of critical dimension features, such aspolysilicon gate electrodes in integrated circuits. While the use of twophotomasks, and thus two exposure steps, is of course cumbersome in themanufacture of integrated circuits, the incorporation of phase-shiftmasking for critical dimension features along with conventional maskingfor the non-critical dimension features, into a single photomask, hasbeen found to be extremely difficult, and unsuitable for automated maskgeneration. The above-noted U.S. Pat. No. 5,858,580 describes a knowntwo-photomask photolithographic process. According to this technique,one photomask, referred to as the “phase shift” mask, defines thecritical dimension features through the use of adjacent phase-shiftapertures therethrough. These critical dimension features, in the caseof the polysilicon gate level, are typically located over “active”regions of the integrated circuit wafer, so that the patterned gateelectrodes thereat serve as transistor gates. The other photomask,referred to as the “binary” mask, defines features of the level that arenot critical dimension, and that do not require phase-shift masking; assuch, the binary mask does not include phase-shift apertures. The binarymask also masks the phase-shift-exposed locations of the wafer, so asnot to interfere with the phase-shift exposure of the critical dimensionfeatures. According to this technique, photolithography is carried outby exposing the wafer first through either the binary mask or the phaseshift mask, and then (before developing the photoresist) again exposingthe wafer through the other of the paired masks. As a result, thecritical features are formed by way of phase-shift masking, while easingthe generation of the photomasks themselves so as to comply with thedesign rules of the integrated circuit.

[0011] It has been observed, in connection with the present invention,that certain difficulties are present in the fabrication of integratedcircuits using the two-photomask method, such as described by way ofexample in the above-noted U.S. Pat. No. 5,858,580. These difficultieswill now be described relative to FIGS. 1a through 1 f.

[0012]FIGS. 1a and 1 b illustrate, in plan and cross-sectional views,respectively, an exemplary structure to be formed at the polysilicongate level in an integrated circuit, relative to which difficultiesfaced with conventional phase-shift photolithography will be describedwith reference to FIGS. 1c through 1 g. This structure is formed at asurface of silicon substrate 2 at which field oxide structure 8 ispresent, adjacent to active region 4 at which transistors will beformed. As is well-known in the art, active region 4 is defined by thoselocations of the surface of substrate 2 at which field oxide 8 is notpresent, such that field oxide 8 serves as an isolation structure.Polysilicon gate electrode 6 g and polysilicon conductor 6 c are formedfrom the same deposited polysilicon layer, patterned by way ofphase-shift photolithography as will be described below. Gate electrode6 g is of course disposed over active region 4 (separated therefrom bygate dielectric 7, in the conventional manner), and slightly overlapsonto field oxide 8; in this way, in operation, voltage applied to gateelectrode 6 g will control conduction between the opposing sides ofactive region 4 (which will be doped to form the transistor source anddrain). Conductor 6 c, in this location of the integrated circuit, isdisposed on field oxide 8, and serves as a signal conductor. Accordingto this example, gate electrode 6 g is a critical dimension feature,meaning that it is to be formed to have a very narrow (e.g., on theorder of 0.15 μ) width so as to provide a high performance transistor.Conductor 6 c, on the other hand, is formed of a non-critical width(e.g., 0.5 μ or greater).

[0013]FIGS. 1c and 1 e illustrate portions of a pair of photomasks 13,15 used to pattern gate electrode 6 g and conductor 6 c according to aconventional technique, similar to that described in the above-notedU.S. Pat. No. 5,858,580, for the case where positive photoresist is used(i.e., exposed photoresist to be removed in developing). As noted above,photomasks 13, 15 may either be reticles, or 1X photomasks. Typically,however, in modern photolithography of sub-micron features such as inthis example, photomasks 13,15 will be reticles.

[0014] Phase shift photomask 13, illustrated in FIG. 1c, utilizes thephase-shift technique noted above to pattern critical dimension gateelectrode 6 g. As shown in FIG. 1c, phase shift photomask 13 includesapertures 10 ₀, 10 _(π), which are disposed on opposite sides of thelocation at which gate electrode 6 g is to be formed. Apertures 10 ₀, 10_(π) are constructed so that they transmit light of opposite phaserelative to one another.

[0015]FIG. 1d illustrates, in cross-section, the portion of phase shiftphotomask 13 that includes apertures 10 ₀, 10 _(π). Phase shiftphotomask 13 includes quartz substrate 11, upon which chrome film 9defines the location of apertures therethrough, such as apertures 10 ₀,10 _(π). According to this conventional approach, apertures 10 ₀, 10_(π) are realized not only by the absence of chrome film 9, but also bythe depth to which a recess or trench is etched into quartz substrate 5thereat. In this example, aperture 10 _(π), is formed by a recess etchedinto quartz substrate 11, while aperture 10 ₀ is simply an opening inchrome film 9. The depth of the recess of aperture 10 _(π) is selectedso that the remaining relative thicknesses t₀, t_(π), of substrate 11 atapertures 10 ₀, 10 _(π) respectively, correspond to the desired relativephase of light passing therethrough (considering the transmitted lightto be locally coherent, as noted above). These thicknesses t₀, t_(π),depend upon the wavelength of the light to be used in the exposure, asis known in the art. In this case, the light transmitted by aperture 10_(π) will have a 180° (π radians) phase shift relative to the lighttransmitted by aperture 10 ₀.

[0016] Referring back to FIG. 1c, phase shift photomask 13 does notexpose photoresist at any other locations than at the critical-dimensionlocations, according to this conventional approach. In particular, it isapparent from a comparison of FIG. 1a to FIG. 1c that phase shiftphotomask 13 does not expose the region between gate electrode 6 g andconductor 6 c, nor does it expose much of active region 4 on either sideof gate electrode 6 _(g). As such, phase shift photomask 13 is typicallyreferred to as a “dark field” mask. According to conventional two-maskphase shift photolithography, phase shift photomasks such as photomask13 do not have apertures that are not directly over active regions, suchas active region 4.

[0017] Binary photomask 15 exposes photoresist regions at thenon-critical dimension locations of the integrated circuit, as evidentfrom FIG. 1e. In this example, binary photomask 15 includes chromeregions 12 g, 12 c that mask exposure at the locations of gate electrode6 g and conductor 6 c; photomask 15 is transparent at the other regions,and as such is commonly referred to as a “bright field” or “light field”photomask. Chrome region 12 g operates as substantially a gateprotective mask, and is not formed to the critical dimension; rather,chrome region 12 g simply protects the region of photoresist that hasbeen, or will be, exposed through photomask 13 from additional exposure,relying on phase shift photomask 13 to define gate electrode 6 g. Chromeregion 12 g does, however, define the end of gate electrode 6 g thatextends toward conductor 6 c, considering that adjacent 0° and 180°phase shift apertures could not so define an exposed region (because ofthe phase cancellation effects). Chrome region 12 c defines conductor 6c, as this feature is not of critical dimension.

[0018] In the manufacture of the structure of FIGS. 1a and 1 b, as iswell known in the art, a photoresist layer (positive resist, in thisexample) is dispensed over the previously deposited polysilicon layerfrom which gate electrode 6 g and conductor 6 c are to be formed. Thewafer and photoresist will then be sequentially exposed to light of thedesired wavelength (e.g., ultraviolet) through photomasks 13, 15. Asdescribed in the above-noted U.S. Pat. No. 5,858,580, the order in whichphotomasks 13, 15 are used is not important. Following this secondexposure, the photoresist layer is developed, with the locations ofphotoresist that were exposed through photomasks 13, 15 being removed,and the unexposed regions remaining to serve as a mask for etch of thepolysilicon.

[0019] A common problem encountered in photolithography is the presenceof low contrast regions of the pattern, such as between gate electrode 6g and conductor 6 c in this example, at which bridging of the etchedpolysilicon may result. FIG. 1f illustrates the results of a simulationof the magnitude of light exposure for the case of double exposurethrough photomasks 13, 15, as described hereinabove. In this particularexample, the critical dimension width of gate electrode 6 g isapproximately 0.16 μ, and the space between the end of gate electrode 6g and conductor 6 c is approximately 0.12 μ, as evident from FIG. 1f.

[0020]FIG. 1f illustrates that the central location at which gateelectrode 6 g is to be formed receives no light exposure, nor does thelocation of conductor 6 c (the no exposure regions represented by thecross-hatching). Locations on either side of the location of gateelectrode 6 g receive full exposure (indicated by the absence ofhatching). FIG. 1f also includes contour lines, each representative oflocations receiving common exposure levels, and each corresponding to a10% step from full exposure to no exposure. As evident from FIG. 1f, theregion between the end of gate electrode 6 g and conductor 6 c does notreceive full exposure as it ought to (polysilicon is to be etched fromthis location, as shown in FIG. 1a); rather, this region receives on theorder of 60% of full exposure. This reduced exposure is due to the smallspacing between chrome regions 12 c, 12 g of binary photomask 15.Because of this reduced exposure, some amount of photoresist may remainat this location after exposure and developing, particularly consideringsuch factors as photoresist thickness and topography due to field oxidestructure 8 at this location. As a result, the etch of polysiliconbetween gate electrode 6 g and conductor 6 c may be incomplete, causingbridging and shorting between these two elements. Because conventionaldouble photomask phase shift lithography has been concerned with thedefinition of critical dimension features such as gate electrode 6 g,this conventional approach does not provide relief for this problem.

[0021] By way of further background, phase shift masks having oppositeand intermediate phase regions are also known in the art. FIG. 1gillustrates phase shift photomask 17 according to this conventionalapproach, for the example of the structure of FIGS. 1a and 1 b. As shownin FIG. 1g, photomask 17 includes chrome regions 16 g, 16 c, that maskthe locations at which gate electrode 6 g and conductor 6 c are to beformed. Apertures 18 in photomask 17, however, have one of four possiblephase shifts, and are arranged so as to provide phase cancellation atthe critical dimension of gate electrode 6 g, while permitting exposureof the end of gate electrode 6 g that extends toward conductor 6 c (FIG.1a). In the example of FIG. 1g, apertures 18 ₀, 18 ₁₈₀ are on opposingsides of chrome region 16 g, and transmit opposite phase light relativeto one another. On the end of chrome region 16 g toward chrome region 16c, however, photomask 17 includes adjacent apertures 18 ₆₀, 18 ₁₂₀,which transmit light at 60° and 120° phase angles relative to the lighttransmitted through aperture 18 ₀. Aperture 18 ₆₀ is disposed betweenapertures 18 ₀ and 18 ₁₂₀, and aperture 18 ₁₂₀ is disposed betweenapertures 18 ₆₀ and 18 ₁₈₀, as shown in FIG. 1g. While this gradation ofphase shift through apertures 18 provides adequate exposure, in manycases, for structures such as that shown in FIGS. 1a and 1 b, suchmultiple phase photomasks are extremely expensive to fabricate, are notconducive to automated photomask generation, and also presentsignificant difficulty to focusing of the exposure in thephotolithography process.

BRIEF SUMMARY OF THE INVENTION

[0022] It is therefore an object of the present invention to provide aphotolithography method in which critical dimension features may befabricated in close proximity to other features, while providingadequate exposure therebetween.

[0023] It is a further object of the present invention to provide such aphotolithography method which utilizes a pair of photomasks for theexposure.

[0024] It is a further object of the present invention to provide such aphotolithography method which does not require more than opposite phaseapertures.

[0025] It is a further object of the present invention to provide such aphotolithography method in which the fabrication of small features isimproved.

[0026] Other objects and advantages of the present invention will beapparent to those of ordinary skill in the art having reference to thefollowing specification together with its drawings.

[0027] The present invention may be implemented in a two-photomasksystem for exposing photoresist in the photolithography of a singlefunctional level in an integrated circuit. One photomask serves as thebinary photomask, and includes masking structures that mask the exposureof non-critical dimension features, as well as protecting criticaldimension features from exposure. The phase shift photomask includesopposite phase apertures for the exposure of critical dimensionfeatures. Additionally, the phase shift photomask includes additional,non-phase-shift, apertures corresponding to locations at whichinadequate exposure is possible, such as at locations between adjacentstructures.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0028]FIGS. 1a and 1 b are plan and cross-sectional views, respectively,of a portion of an exemplary integrated circuit structure, at thepolysilicon gate level, to be formed by way of photolithography.

[0029]FIGS. 1c and 1 d are plan and cross-sectional views, respectively,of a portion of a phase shift photomask used in the photolithography ofthe structure of FIGS. 1a and 1 b, according to a conventionaltechnique.

[0030]FIG. 1e is a plan view of a portion of a binary photomask used inthe photolithography of the structure of FIGS. 1a and 1 b, according toa conventional technique.

[0031]FIG. 1f is a simulation plot of exposure according to conventionalphotolithography using the photomasks of FIGS. 1c through 1 e.

[0032]FIG. 1g is a plan view of a portion of a phase shift photomaskused in the photolithography of the structure of FIGS. 1a and 1 b,according to another conventional technique.

[0033]FIG. 2a is a plan view of a portion of a binary photomask used inthe photolithography of the structure of FIGS. 1a and 1 b, according toa first preferred embodiment of the present invention.

[0034]FIG. 2b is a plan view of a portion of a phase shift photomaskused in the photolithography of the structure of FIGS. 1a and 1 b,according to the first preferred embodiment of the present invention.

[0035]FIG. 2c is a simulation plot of exposure according tophotolithography using the photomasks of FIGS. 2a and 2 b according tothe first preferred embodiment of the present invention.

[0036]FIGS. 3a and 3 b are plan views of a portion of photomasks used inthe photolithography of the structure of FIGS. 1a and 1 b, according toa second preferred embodiment of the present invention.

[0037]FIG. 3c is a simulation plot of exposure according tophotolithography using the photomasks of FIGS. 3a and 3 b according tothe second preferred embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0038] As will be apparent to those of ordinary skill in the art havingreference to this specification, the present invention may be realizedby way of the construction of photomasks for use in the fabrication ofintegrated circuits, and the use of such photomasks in such fabrication.As is well known in the art and as discussed above, photomasks in thefield of integrated circuit manufacture appear in many different forms,including “1X” photomasks on which the mask features are the same sizeas the features to be imaged on the integrated circuit wafers, and alsoreticles which typically have features that are some multiple (e.g., 4X)of the size of the features to be imaged on the wafer, thus requiring alens system to focus the exposure onto the wafer. Furthermore, modemphotolithography is typically carried out by way of steppers, where eachintegrated circuit die (or small array of die) on a wafer is separatelyimaged, and the wafer is “stepped” or indexed (relative to the photomaskor reticle) to the next die position on the wafer for imaging of thenext die or array of die. Of course, particularly for smaller wafersizes or for less than minimum geometries, the photomask may image theentire wafer surface with a single exposure. It is contemplated that thepresent invention may be realized with benefit in each of theseapplications. Accordingly, for purposes of the following description,the term “photomask” is intended to refer to each and all of theserealizations.

[0039] As is fundamental in photolithography, photomasks are used toselectively expose portions of a photosensitive film, typicallyphotoresist, that is in place at the surface of an integrated circuitwafer. As is known in the art, photoresists may be of the positive ornegative type. By way of definition, the term negative photoresistrefers to photoresist material that polymerizes upon exposure anddevelopment, with the unexposed regions of photoresist being removedfrom the wafer, while positive photoresist refers to photoresist that,when exposed and developed, is selectively removable from the wafer withthe unexposed regions of photoresist remaining thereupon. It iscontemplated that the present invention may be used in the exposure andimaging of either type of resist. However, the present invention iscontemplated to be particularly beneficial when applied to thephotolithography of positive photoresist, as will be evident from thefollowing description.

[0040] Referring now to FIGS. 2a and 2 b, a photomask arrangementaccording to a first preferred embodiment of the present invention willnow be described in detail. The photolithography and correspondingphotomasks according to this first preferred embodiment of the inventionare intended for the formation of an elongated conductor of anintegrated circuit of minimum feature size, or critical dimension. Byway of example, photomasks 25, 23 (portions of which are shown in FIGS.2a and 2 b, respectively) according to this first preferred embodimentof the invention will be described relative to the photolithographicfabrication of polysilicon gate electrode 6 g near polysilicon conductor6 c in the structure illustrated in FIGS. 1a and 1 b describedhereinabove. Of course, it is contemplated that the first preferredembodiment of the invention may be used in connection with thephotolithography of other films, such as metallization layers, silicidefilms, and the like. Additionally, as will become apparent from thefollowing description, photomasks 23, 25 according to this firstpreferred embodiment of the present invention are to be used inconnection with positive photoresist.

[0041]FIG. 2a illustrates a portion of binary photomask 25 according tothis first preferred embodiment of the invention. Binary photomask 25 isconstructed in the conventional manner to have a quartz substrate, uponwhich a chrome film is deposited and patterned (for example, by way ofphotolithography) to define its transparent and opaque (i.e., masking)regions. In this embodiment of the present invention, in the portion ofbinary photomask 25 illustrated in FIG. 2a, chrome regions 22 g, 22 care provided to block the photo-exposure of photoresist at the locationsof gate electrode 6 g and conductor 6 c, with aperture 24 referring tothe transparent portion of binary photomask 25 between and around chromeregions 22 g, 22 c. According to this first preferred embodiment of theinvention, the phase of light transmitted through aperture 24 is notimportant, and as such aperture 24 may be formed simply by the removalof chrome at its location (i.e., a recess or trench, to effect aparticular phase shift, is not required for aperture 24).

[0042] Considering that gate electrode 6 g will be defined by way ofphase shift photomask 23 (described below), chrome region 22 g extendssomewhat beyond the lateral boundaries of the location at which gateelectrode 6 g is to be formed. In this manner, chrome region 22 g as agate protective mask, ensuring that gate electrode 6 g is formed only bythe exposure through phase shift photomask 23, and need not be formed asa critical dimension feature. Chrome region 22 c, on the other hand,defines the location of conductor 6 c, and as such is defined to thedesired dimensions and location of this feature. In this regard, andconsidering that photomasks 23, 25 according to this example are used inconnection with positive photoresist, binary photomask 25 may bereferred to as a “bright field” or “light field” photomask.

[0043]FIG. 2b illustrates a corresponding portion of phase shiftphotomask 23 according to this first preferred embodiment of the presentinvention. Phase shift photomask 23 is fabricated in similar fashion asdescribed above relative to binary photomask 25, by way of patternedchrome film disposed upon a quartz substrate; in addition, however,certain of the apertures in phase shift photomask 23 are formed by wayof recesses or trenches etched into the quartz substrate in order toprovide opposing phase relationships, as will be described below. Inthis regard, as illustrated in FIG. 2b, phase shift photomask 23includes apertures 20 ₀, 20 _(π) through chrome film 29 at locationsalong opposite sides of the location at which gate electrode 6 g is tobe formed. Apertures 20 ₀, 20 _(π) are formed in phase shift photomask23 so that the light transmitted by aperture 20 _(π) will have a 180° (πradians) phase shift relative to the light transmitted by aperture 20 ₀.Of course, while exactly a 180° phase shift is preferable in order toprovide the optimum cancellation effects, some amount of error istolerable in the actual phase shift that is produced.

[0044] As described above, light at a particular wavelength issubstantially locally coherent when transmitted through photomaskapertures of a size that is on the same order as the wavelength itself.The phase of the transmitted light depends upon the thickness of thetransparent substrate traversed by the transmitted light. In thisregard, apertures 20 ₀, 20 _(π) of phase shift photomask 23 according tothis first preferred embodiment of the invention transmit light ofopposite phase relative to one another, so that the critical dimensionof the width of gate electrode 6 g may be precisely defined bywell-known phase cancellation effect.

[0045] As is known in the art, diffraction effects cause thephotoexposure through a mask to not precisely align with the edges ofopaque features of the photomask. As the feature being patterned becomesvery small, for example in the case of a very small opaque feature of aphotomask defining a region, such as a gate electrode, that is not to beexposed in photolithography, diffracted light from opposite sides of theopaque photomask may overlap at the photoresist location beneath theopaque mask feature. In this event, the desired feature may not beimaged in the photoresist. Phase shift photolithography, for example asimplemented by phase shift photomask 23 in this embodiment of theinvention, provides opposite phase apertures on opposite sides of theopaque chrome region, so that overlapping diffracted light cancels out.

[0046] Referring back to FIG. 2b, this phase cancellation effect occursbecause the opposite phase light transmitted through apertures 20 ₀, 20_(π) relative to one another cancels out at locations between apertures20 ₀, 20 _(π), rendering the photoresist unexposed. As described aboverelative to conventional phase shift masks, in order to cause the lighttransmitted through apertures 20 ₀, 20 _(π) to be of opposite phaserelative to one another, apertures 20 ₀, 20 _(π) are realized not onlyby the absence of chrome film 29 thereat, but also differences in thethickness of the underlying substrate at the aperture locations.Conventionally, phase shift mask apertures such as apertures 20 ₀, 20_(π) are formed by etching trenches into the quartz substrate 5 at oneor both of apertures 20 ₀, 20 _(π) so that the remaining thicknesses ofthe substrate at apertures 20 ₀, 20 _(π) differ from one another. Asdiscussed above, the relationship between the substrate thicknessesdepends upon the wavelength of the light to be used in the exposure.According to known theory, the differential thickness, or trench depth,to provide a full 180° phase shift for light of wavelength λ is(2N+1)λ/2n with N an integer (0, 1, 2, . . . ) and n the index ofrefraction of the mask substrate, which is 1.45 for quartz. For example,if the light used to expose photoresist through photomask 23 has awavelength of 248 nm, differential trench depth values of 85.5 nm, 256.5nm, 427 .5 nm, . . . , between adjacent apertures 20 ₀, 20 _(π) wouldprovide the opposite phase effect.

[0047] According to this first preferred embodiment of the invention,phase shift photomask 23 includes additional aperture 30 through chromefilm 29. Aperture 30 is disposed at a location between the eventual endof gate electrode 6 g and the eventual location of polysilicon conductor6 c. With reference to FIG. 1a, aperture 30 is disposed over field oxidestructure 8; this location of an aperture in a phase shift photomask iscontrary to the arrangement of conventional phase shift photomasks, inwhich apertures are limited to active region locations. In thispreferred embodiment of the invention, aperture 30 is preferably formedto have a width so as not to overlap onto either of the intendedlocations of gate electrode 6 g and conductor 6 c. The particularprecision of the spacing of aperture 30 from these intended featureedges is not particularly critical, however. Also according to thisfirst preferred embodiment of the invention, the phase shift applied byaperture 30 to light transmitted therethrough is of no importance; assuch, aperture 30 may be formed, in this example, as either a zero phaseshift aperture or a 180° phase shift aperture. For ease of manufacture,aperture 30 may be formed on photomask 23 by simply etching an aperturethrough chrome film 29, without formation of a recess into the masksubstrate.

[0048] In the use of photomasks 23, 25 according to the presentinvention in the photolithography process, an integrated circuit waferhaving a polysilicon layer deposited thereupon is coated with a positivephotoresist. The coated wafer is then exposed twice, in thephotolithography process for this level of polysilicon. One exposure ismade through binary photomask 25, and the second through phase shiftphotomask 23. The order in which these two exposures is carried out isnot important, as there is not believed to be any dependence of theresulting exposure of the photoresist upon the order in which photomasks23, 25 are used. Following both exposures, the photoresist is developed.Polysilicon etch is then carried out, by way of a wet etch or a plasmaetch (plasma etch being preferably for the critical dimension gateetch), using the remaining unexposed portions of the photoresist layeras a mask to the etch. Following the etch, the photoresist mask isremoved, and the wafer continues through the manufacturing process.

[0049] The effect of aperture 30 in the formation of gate electrode 6 gand conductor 6 c, particularly in consideration of the edge of fieldoxide structure 8 therebetween (see FIGS. 1a and 1 b), is to provideadditional exposure to the photoresist at this location. As discussedabove relative to FIG. 1f, the combination of the phase cancellationeffects and the close proximity of the two polysilicon elements (the endof critical dimension gate electrode 6 g and non-critical dimensionconductor 6 c) can result in the underexposure of the photoresistbetween these elements, and in the resulting bridging of polysilicon inthis location. Aperture 30 provides additional exposure to thisotherwise underexposed location, thus ensuring full exposure andeliminating the possibility of bridging thereat.

[0050]FIG. 2c illustrates the results of an exposure simulation for theportions of photomasks 23, 25 used to fabricate gate electrode 6 g andconductor 6 c in the structure of FIGS. 1a and 1 b. In this plot,regions that receive no exposure, such as at the locations of gateelectrode 6 g and conductor 6 c, are cross-hatched, while locationsreceiving full exposure, such as generally within the locations ofapertures 20 ₀, 20 _(π), are blank. The contour lines connect pointsreceiving common exposure levels, at 10% increments between fullexposure and no exposure. FIG. 2c also illustrates the location ofaperture 30 in this simulation.

[0051] As shown in FIG. 2c, as a result of the incorporation of aperture30 into phase shift photomask 23 according to this first preferredembodiment of the invention, the region between the end of gateelectrode 6 g and conductor 6 c now receives full exposure over a largepart of its width. Comparison of the simulation of FIG. 2c with thatillustrated in FIG. 1f according to conventional two-mask phase shiftphotolithography shows significant improvement in the exposure of thiscritical region. As a result of the present invention, therefore, therisk of inadequate exposure resulting in bridging of the patterned film,such as polysilicon in this example, is greatly reduced if not fullyeliminated.

[0052] This important benefit of the present invention is obtained ateffectively no cost in either the manufacturing of the photomasks or ofthe integrated circuit wafers themselves. Additional aperture 30 inphase shift photomask 23 in this embodiment of the invention may beformed at effectively no cost, especially considering that its phaseshift effect is not relevant to the operation of the invention (and thusno trench or recess need be formed thereat). Furthermore, consideringthat two exposures are being used to pattern the critical dimension gateelectrode 6 g in this polysilicon layer, the inclusion of aperture 30 inphase shift photomask 23 does not add to the manufacturing cost of thewafer in any way. As such, the present invention provides improvedpatterning at minimal incremental cost over conventional two-maskphotolithography.

[0053] It is contemplated that the automated generation of photomasks toinclude additional apertures according to the present invention may bereadily performed. For example, the photomask generation program canreadily identify wafer locations that have a spacing below a certainthreshold value, in a particular level for which two-mask exposure usingbinary and phase shift masks is to be performed. At these identifiedlocations, the photomask generation program can then insert an aperturein the phase shift photomask; for ease of manufacture, this additionalaperture may simply be made to have the same phase as the nearest phaseshift aperture.

[0054] The present invention may also be used to benefit in thefabrication of other structures, particularly those that are relativelysmall features, whether isolated or interspersed among other unrelatedfeatures. An example of the photolithographic fabrication of a “post”feature, for example of polysilicon, according to a second preferredembodiment of the present invention will now be described relative toFIGS. 3a and 3 b. In this regard, it is contemplated that the example ofthe application of the second preferred embodiment of the invention asillustrated relative to FIGS. 3a and 3 b will be carried out at anotherlocation of the wafer utilizing a double exposure phase shift masking,for example as described above relative to FIGS. 2a through 2 c or evenin combination with conventional techniques, in which a two-maskphotolithographic operation is already being carried out.

[0055]FIG. 3a illustrates a portion of dark field photomask 33 forforming a polysilicon post at a relatively isolated location of asemiconductor wafer. Such a polysilicon post feature may be useful formaking interlevel connections between an overlying conductor and a lowerconductive region, for example a lower polysilicon level or an activeregion of the underlying substrate. Because of its “dark field”characteristics, it is contemplated that photomask 33 will correspond toa phase shift photomask such as phase shift photomask 23 describedabove, but where the phase shift masking is carried out at a locationseparate from that shown in FIG. 3a. As shown in FIG. 3a, photomask 33includes a chrome field 32, within which aperture 31 is formed so as toleave chrome field 34 near its center. The phase characteristics ofaperture 31 are not important. Chrome field 34 is arranged to besubstantially rectangular, with one dimension somewhat longer than theother, as shown in FIG. 3a. For this example, it is contemplated thatthe width w₃₄ of chrome field 34 is a minimum dimension for dark fieldphotomask 33, for example being on the same order of magnitude as apolysilicon transistor gate electrode width in the integrated circuit.

[0056]FIG. 3b illustrates the same location of bright field photomask 35corresponding to dark field photomask 33 of FIG. 3a. Bright fieldphotomask 35 corresponds to binary photomask 25 described hereinabove,which defines the outline of non-critical dimension features in theintegrated circuit, and as such is contemplated to not include phaseshift masking features. As shown in FIG. 3b, bright field photomask 35has chrome field 36 for masking a portion of the photoresistcorresponding to the post feature to be formed. As in the case of chromefield 34, chrome field 36 has one dimension that is substantially longerthan the other, with the smaller dimension (width w₃₆) being on theorder of the minimum dimension of the level being patterned. Theorientation of chrome field 36 is perpendicular to that of chrome field34, but concentric with the location of chrome field 34, as indicated bythe dashed-line shadow of chrome field 34 in FIG. 3b.

[0057] In use, dark field photomask 33 and bright field photomask 35 areused in the double-exposure of a photoresist film dispensed over aconductive layer, such as polysilicon, that is in place at a surface ofa semiconductor wafer and that is to be etched according to a desiredpattern. In this double-exposure, each of photomasks 33, 35 are ofcourse aligned and registered with the wafer in the appropriate mannerto form the integrated circuit. Such alignment should align photomasks33, 35 with one another, in their separate exposures, in the mannerindicated in FIGS. 2a and 2 b. For example, chrome region 22 g of binaryphotomask 35 is to cover the opaque spacer between openings 20 ₀, 20_(π) of phase shift photomask 33. As before, the order in which thephotoresist layer is exposed through photomasks 33, 35 is not important.It is also preferred, as noted above, that dark field photomask 33include phase shift apertures elsewhere in the integrated circuit,considering that two exposures are being made anyway; preferably, darkfield photomask 33 includes additional apertures, such as aperture 30,at potential bridging locations, as described hereinabove relative tothe first preferred embodiment of the invention. As a result of thedouble exposure of photoresist through photomasks 33, 35, an unexposedportion of photoresist will be present at the location corresponding tothe intersection of chrome field 34 and chrome field 36. This unexposedportion of the photoresist will remain after developing, serving as amask during the etch of the underlying layer. A post of this layer willbe formed accordingly.

[0058]FIG. 3c illustrates the results of an exposure simulation relativeto the double exposure of a photoresist layer through photomasks 33, 35,where boundary 38 corresponds to the intersection of chrome regions 34,36, and for the example where critical dimension widths w₃₄ and w₃₆ areeach 0.2 μ. In this simulation, exposure levels range from full exposurein region 37 surrounding boundary 38, to no exposure at the center ofboundary 38 (no cross-hatching being present in FIG. 3c, for purposes ofclarity). Contour lines in FIG. 3c connect points of equal exposure, at10% intervals from full exposure to no exposure, where contour line 39corresponds to the boundary of no exposure. By way of comparison,contour line 39′ is shown in FIG. 3c to indicate the no exposureboundary from simulation of a single exposure using a square chromemasking element of dimensions equal to the intersection of chromeregions 34, 36 (i.e., corresponding to boundary 38).

[0059] As is readily apparent from FIG. 3c, the formation of aphotoresist feature, and thus a resulting underlying integrated circuitfeature, using a double exposure approach according to this secondembodiment of the present invention is improved by the use ofperpendicular chrome regions on the two photomasks. This improvementresults from the use of the chrome regions of the two masks, angledrelative to one another (in this case substantially perpendicularly),preventing the overexposure that occurs from the single masking element.As a result, minimum feature size mask elements may be used to formisolated features of reliable construction, without requiring oversizingof the mask elements.

[0060] It is contemplated that additional alternative embodiments of thepresent invention will also become apparent to those of ordinary skillin the art having reference to this specification, while still obtainingthe benefits of the present invention. In this regard, it iscontemplated that the benefits provided from use of the second exposurephase shift mask for the patterning of binary elements according to thepresent invention, such as described hereinabove, can be applied in manycircumstances in the manufacture of modern integrated circuits.

[0061] While the present invention has been described according to itspreferred embodiments, it is of course contemplated that modificationsof, and alternatives to, these embodiments, such modifications andalternatives obtaining the advantages and benefits of this invention,will be apparent to those of ordinary skill in the art having referenceto this specification and its drawings. It is contemplated that suchmodifications and alternatives are within the scope of this invention assubsequently claimed herein.

We claim:
 1. A method of fabricating an integrated circuit, comprisingthe steps of: applying a photosensitive material at a surface of asemiconductor wafer; exposing the photosensitive material toelectromagnetic energy through a binary photomask, the binary photomaskhaving a plurality of opaque regions at a surface thereof to blockselected locations of the photosensitive material from exposure to theelectromagnetic energy, the plurality of opaque regions including firstand second opaque regions disposed near one another and defining a firstaperture therebetween through which the photosensitive material isexposed to the electromagnetic energy; and exposing the photosensitivematerial to electromagnetic energy at a selected wavelength through aphase shift photomask, the phase shift photomask having an opaque filmat a surface thereof in which a plurality of apertures are formed todefine locations at which the photosensitive material is exposed to theelectromagnetic energy, the plurality of apertures including first andsecond phase shift apertures separated from one another on the photomaskby a first opaque region of the opaque film, the first phase shiftaperture constructed to transmit electromagnetic energy at substantiallyan opposite phase from the electromagnetic energy transmitted by thesecond phase shift aperture, and the plurality of apertures alsoincluding a third aperture in the opaque film separated from the firstand second phase shift apertures; wherein the binary photomask and thephase shift photomasks are aligned in their respective exposing steps sothat the first opaque region of the phase shift photomask corresponds toa first integrated circuit location that also corresponds to the firstopaque region of the binary photomask; and wherein the binary photomaskand the phase shift photomasks are aligned in their respective exposingsteps so that the third aperture of the phase shift mask corresponds toa second integrated circuit location that also corresponds to the firstaperture of the binary photomask.
 2. The method of claim 1, wherein theapplying step applies the photosensitive material over a conductivelayer at the surface of the wafer; and further comprising: after theexposing steps, developing the photosensitive material to removeportions thereof defined in the exposing steps, to expose portions ofthe conductive layer; and after the developing step, etching the exposedportions of the conductive layer.
 3. The method of claim 2, wherein thedeveloping step removes portions of the photosensitive material thatwere exposed to electromagnetic energy in the exposing steps.
 4. Themethod of claim 3, wherein the conductive layer comprises polysilicon.5. The method of claim 4, wherein the first integrated circuit locationcorresponds to a polysilicon gate electrode.
 6. The method of claim 5,wherein the second opaque region of the binary photomask corresponds toa polysilicon conductor.
 7. The method of claim 6, wherein theconductive layer comprising polysilicon is disposed over an activeregion of the integrated circuit wafer and also over a field oxidestructure of the integrated circuit wafer; wherein the first integratedcircuit location corresponds to a polysilicon gate electrode overlyingthe active region; and wherein the second opaque region of the binaryphotomask corresponds to a polysilicon conductor overlying the fieldoxide structure.
 8. The method of claim 7, wherein the second integratedcircuit location corresponds to a location overlying the field oxidestructure.
 9. The method of claim 1, wherein the step of exposing thephotosensitive material to electromagnetic energy at a selectedwavelength through the phase shift photomask is performed after the stepof exposing the photosensitive material to electromagnetic energythrough the binary photomask.
 10. The method of claim 1, wherein thestep of exposing the photosensitive material to electromagnetic energythrough the binary photomask is performed after the step of exposing thephotosensitive material to electromagnetic energy at a selectedwavelength through the phase shift photomask.
 11. The method of claim 1,wherein the plurality of opaque regions of the binary photomask alsoincludes a third opaque region, having a rectangular shape with a firstdimension longer than a second dimension; wherein the plurality ofapertures of the phase shift mask also define a second opaque regionhaving a rectangular shape with a first dimension longer than a seconddimension; and wherein the binary photomask and the phase shiftphotomask are aligned in their respective exposing steps to define athird integrated circuit location corresponding to the intersection ofthe third opaque region of the binary photomask and the second opaqueregion of the phase shift mask, the third opaque region of the binaryphotomask and the second opaque region of the phase shift mask beingaligned orthogonal to one another so that the third integrated circuitlocation has a size defined by the second dimension of each of the thirdopaque region of the binary photomask and the second opaque region ofthe phase shift mask.
 12. A set of photomasks for photolithographicpatterning of a layer of an integrated circuit, comprising: a binaryphotomask having a plurality of opaque regions at a surface thereof, theplurality of opaque regions including first and second opaque regionsdisposed near one another and defining a first aperture therebetween; aphase shift photomask having an opaque film at a surface thereof inwhich a plurality of apertures are formed, the plurality of aperturesincluding first and second phase shift apertures separated from oneanother on the photomask by a first opaque region of the opaque film,the first and second phase shift apertures constructed to transmitelectromagnetic energy at substantially opposite phases relative to oneanother, and the plurality of apertures also including a third aperturein the opaque film separated from the first and second phase shiftapertures; wherein the first opaque region of the phase shift photomaskcorresponds to a first integrated circuit location that also correspondsto the first opaque region of the binary photomask; and wherein thethird aperture of the phase shift mask corresponds to a secondintegrated circuit location that also corresponds to the first apertureof the binary photomask.
 13. The set of photomasks of claim 12, whereinthe plurality of opaque regions of the binary photomask also includes athird opaque region, having a rectangular shape with a first dimensionlonger than a second dimension; wherein the plurality of apertures ofthe phase shift mask also define a second opaque region having arectangular shape with a first dimension longer than a second dimension;and wherein the intersection of the third opaque region of the binaryphotomask and the second opaque region of the phase shift mask define athird integrated circuit location, the third opaque region of the binaryphotomask and the second opaque region of the phase shift mask beingaligned orthogonal to one another so that the third integrated circuitlocation has a size defined by the second dimension of each of the thirdopaque region of the binary photomask and the second opaque region ofthe phase shift mask.